06/03/22 23:47:24
>>270
process(CLK)
variable REG1,REG2,REG3 : std_logic;
begin
if(CLK'event and CLK='1') then
REG1 := SIN;
REG2 := REG1;
REG3 := REG2;
SOUT <= REG3;
end if;
end process;
REG1～3をなんに使うかは知らないがｗ
06/03/22 23:47:24
>>270
process(CLK)
variable REG1,REG2,REG3 : std_logic;
begin
if(CLK'event and CLK='1') then
REG1 := SIN;
REG2 := REG1;
REG3 := REG2;
SOUT <= REG3;
end if;
end process;
REG1～3をなんに使うかは知らないがｗ