09/09/11 00:17:02 gMJd18aF
URLﾘﾝｸ(software.intel.com)
誰もこれの存在に触れないんだよな
Sandy Bridgeのスペックなにげにネタバレしてるのに
> The IntelR Architecture Code Analyzer does not assume a specific Intel processor with
> an implementation of the Intel AVX instruction set. It models the ports, functional units,
> first level cache latencies, instruction throughputs and latencies of a possible HW implementation.
>
> Among other things the modeled processor has:
>
> * One divide unit attached to port 0.
> * Two 128-bit load ports (2 and 3), each with an Address Generation Unit (AGU) attached to it.
> * One 128-bit store port (port 4).
> * First level cache latencies in a range between 5 and 8 cycles.