PC9821でLINUXをはじめよう!at LINUX
PC9821でLINUXをはじめよう! - 暇つぶし2ch53:login:Penguin
01/11/08 00:28 QNktuDms.net
|  0 GR Color Key Compare|  0 CR H Total     |  1 SR PCI Burst   
|  0 GR DCLK Output 2  | 20 CR Interlace End  |  0 SR Pixel Bus Select
|  0 GR Decreased WE* Act|  0 CR Line Compare   |  0 SR Primary Map Selec
|  0 GR Decreased Write F|  0 CR Multiply V Regist|  0 SR R/W Data   
|  0 GR Dest Write Mask | 50 CR Offset      |  0 SR R/W Data   
|  1 GR ON 8 8 Pattern C|  0 CR Overlay/DAC Mode |  0 SR Readback of CF6
|  0 GR ON BY-8 Addressin|  0 CR Overlay Timing Si|  0 SR Reset Signature G
|  1 GR ON Color Expand |  0 CR Refresh Cycle Con|  0 SR SK to EEPROM (EEP
|  0 GR ON Color Expand w|  0 CR Screen A Preset R|  1 SR Shadow DAC Writes
|  0 GR ON Enhanced Write|  0 CR Screen Start A Ad|  0 SR Secondary Map Sel
|  0 GR ON Eight Byte Dat|  1 CR Select Row-scan C|  0 SR Shift and Load 16
|  1 GR ON Extended Write|  1 CR Timing ON    |  0 SR Shift and Load 32
|  0 GR ON Offset Registe|  0 CR Text Cursor End |  0 SR Signature Generat
|  0 GR Foreground Color | 334 CR Text Cursor Locat|  1 SR Signature Generat
|  0 GR Function Select |  0 CR Text Cursor Skew |  0 SR Sequencer Pixel C
|  1 GR Graphics Mode  |  0 CR Text Cursor Start|  1 SR Synchronous Reset
|  1 GR Memory Map    |  0 CR Underline Scanlin|  1 SR Select High-resol
|  0 GR Odd/Even     | 146 CR V Blank End   |  0 SR These bits are re
|  0 GR Offset 0     | 12c CR V Blank Start  | 3b SR These bits are re
|  0 GR Offset 1     |  0 CR V Display End  |  0 SR VCLK Denominator
|  1 GR Offset Granularit|  0 CR V Sync End    |  f SR VCLK Denominator
|  0 GR Plane Select   | 12e CR V Sync Start   |  d SR VCLK Denominator
|  0 GR Read Mode    | 144 CR V Total     |  0 SR VCLK Denominator
|  0 GR Rotate Count   |  0 CR Write Protect CR7| 4b SR VCLK Numerator
|  0 GR Shift Register Mo|  1 SR 8/9 Dot Clock  |  0 SR VCLK Numerator
|  0 GR Static HSYNC   |  1 SR Asynchronous Rese| 42 SR VCLK Numerator
|  0 GR Static VSYNC   |  0 SR Allow Access to D| 37 SR VCLK Numerator
|  0 GR Write ON     |  0 SR CPU Write Buffer |  0 SR VCLK Post-Scalar
|  0 GR Write Mode 4, 5 F|  1 SR CRT FIFO Depth Co|  0 SR VCLK Post-Scalar
|  0 GR Write Mode 5 Back|  0 SR CS Out to EEPROM |  0 SR VCLK Post-Scalar
|  0 GR Write Mode    |  1 SR Chain-4     |  0 SR VCLK Post-Scalar


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