18/07/08 14:39:10.11 r8hmMT68N BE:19581942-2BP(3)
3.3
Commit
During execution, instructions do not modify the architectural state.
Instead, all changes are buffered and commit together at block completion.
Once the core enters the commit phase, the register file is updated with all register writes, and all stores in the load-store queue are sent to the L1 cache beginning with the lowest sequence identifier.
Once all register writes and stores have committed, the core sends a commit signal to all other cores in the same logical processor.
3.3.1
Refresh
One important commit optimization, called refresh, occurs when the instruction block branches back to itself.
Rather than loading the instructions again from the L1 instruction cache, the instructions are left in place and only the valid bits in the operand buffers and load-store queues are cleared.
This allows the instruction fetch phase to be bypassed entirely.
Instructions that generate constants can also pin values in the operand buffers so that they remain valid after refresh, and are not regenerated each time the instruction block executes.
Element Size Minimum (1 ALU) Maximum (4 ALUs)
8-bit 8 32
16-bit 4 16
32-bit 2 (1 single fp) 8 (4 single fp)
64-bit 1 4
Table 2:
Supported vector operations